Electrical testing will be enhanced to detect soft or weak pixel faults better. The pixel can work with such flaws but cannot reach or maintain the whole voltage level. This impacts the pixel's maximum grayscale level, affecting the test system's maximum signal-to-noise performance.
Fremont, CA: Laptop computers are now possible thanks to flat-panel liquid-crystal displays or LCDs. For desktop computers, they have also started to take the place of cathode-ray-tube monitors. In fact, it is anticipated that the LCD monitor industry will expand quickly throughout the coming years. Low yields and high manufacturing costs have been the main obstacles to the expansion of the LCD market. Elements including display size, resolution, and quality standards have caused lower yield. Quality-control inspection has become more critical than ever for manufacturers.
Focusing on in-process testing and restoration of the thin-film-transistor (TFT) array display component has recently resulted in notable increases in overall yields. Future LCD manufacturers' ability to successfully enter the monitor market will rely on in-process test methodologies that provide the TACT (total cycle) time needed for 100% in-line testing, have a high defect-capture ratio, and have a strong correlation with the types of defects present in the entire display.
Voltage-Imaging-Array Testing
One advantage of the voltage-imaging technique is that it simply requires a shorting bar link to the TFT array to be tested. This eliminates the need for full-contact probe cards, which are costly for most other technologies. By directly measuring the voltage distribution on the indium tin oxide (ITO) TFT pixel rather than at the storage capacitor, voltage imaging assesses the properties of a TFT array. This measurement method mimics the array's actual performance as though it were a TFT cell that has been constructed.
An electro-optic modulator is within 10 to 20 µm of the TFT-array plate being tested. The ITO surface on the electro-optic modulator and the TFT-array plate are connected to a voltage-pattern generator, which generates a voltage potential between the ITO surface and each display pixel on the TFT array. The voltage potential across the modulator controls the intensity of light that passes through it. Diffraction-limited optics is used to image the modulated light onto a 2K x 2K CCD camera.
A measurement picture and a gain-correction image are obtained at every measurement location. The measurement image is subjected to the gain-correction image to adjust for modulator and illumination nonuniformity and scale-modulated light intensity to voltage levels. The image is subjected to a geometrical warping procedure to convert voltages at CCD-pixel resolution into energies at TFT-array pixel resolution. Defective pixels are found by applying user-defined voltage threshold levels to the twisted image. Whether an open or shorted circuit caused the error can be ascertained by postprocessing the faulty pixels. Large regions of voltage change that may result in uneven brightness in the finished display can also be detected by the system, in addition to pixel-level flaws.
The full TFT array is measured by stepping the plate beneath the 70 × 70-mm modulator and taking pictures. As the plate is moved to the subsequent measurement location, the obtained image is processed. The average site-to-site time is 1.8 seconds. In less than 200 seconds, a standard TFT array plate with six 13.3-inch-diagonal panels may be examined.
